The need to manufacture integrated circuits (“IC”) at dimensions ever closer to the fundamental resolution limits of optical lithography systems has made resolution enhancement technologies (“RET”) an integral part of the strategic lithography road map for most very-large-scale integrated (“VLSI”) circuit manufacturers. No longer considered research oriented lithography tricks, these techniques are improving lithography process windows to a point where the current pace of chip integration can be maintained until non-optical lithography solutions become feasible. Along with these improvements come increased complexity at all levels of the IC manufacturing process, and these complexities impact many aspects of chip layout and mask manufacturing as well as wafer processing and characterization.
In current manufacturing processes, the application of RET (e.g., Off Axis Illumination (“OAI”), Optical Proximity Correction (“OPC”), Phase-Shifting Masks (“PSM”)) to subwavelength designs has become a necessary part of manufacturing following tapeout. The RET is necessary in order to make sure that the lithographically printed shapes are as close as possible to the originally targeted, designed layout shapes. However, as a result, design verification processes prior to tapeout have no visibility into whether the designed shapes will actually reach shape closure (the actual design is achieved on silicon), or are RET-able, or manufacturable.
In order to assure shape closure through detail simulation of lithographic processes at the tapeout stage before providing a design to a fabrication facility (“Fab”) or foundry, detail process models and RET recipes of the Fab must be disclosed to the circuit designers for use in RET analysis before tapeout. The lithographic processes include shape-patterning steps, which include for example mask manufacturing, optical exposure, photo resist and other films, resist development, de-scum, etching, chemo-mechanical polishing (“CMP”), etc. While this is expensive from a computational point of view, it is also difficult to achieve logistically because the Foundries typically view the detail modeling and recipes as proprietary information (and Fabs, cumbersome) and therefore are unwilling to disclose such detailed lithographic and manufacturing capabilities. In addition, the designers are unwilling at and incapable of dealing with the complexity and understanding the physics that constraint the design on silicon. Therefore, conventional design verification rules are typically the only means available for use in verifying manufacturability by the way of design rule checking. As such, the state of IC manufacturing is degenerating to a situation where the conventional paradigm and wisdom of rules and heuristics alone can no longer be effective at predicting shape manufacturability. In addition, certain shapes or parts of layout cannot be guaranteed “RET-able” by any of the tools in the conventional design flow. Consequently, there is a need for a tool that enables circuit designers to predict and determine the RET-ability or lithographic manufacturability of a circuit design layout prior to providing the design to the foundry.